Maestrini P.: Breve Storia della CEP. In G. A. Cignoni e F. Gadducci (Eds): La CEP prima della CEP: Storia dell'Informatica, Divulgazione Scientifica e Didattica Sperimentale". Pisa University Pres, 2013.
Chessa S., Maestrini P.: Robust Distributed Storage of Residue Encoded Data. IEEE Transactions on Information Theory, Vol. 58, n.12 (dec. 2012), pp. 7280-7294.
Maestrini P.: Le tecnologie digitali al tempo della CEP. In M. Vanneschi (Ed): La CEP: storia, scienza e umanita` dell`avventura informatica pisana`, pp. 66-93. Felici Editore, Pisa, 2009.
Pessoa Albini L. C., Brawerman A., Nogueira Lima M., Chessa S., Maestrini P. - Virtual structure effects in two hybrid routing protocols for ad hoc networks. IEEE International Symposium on Wireless Pervasive Computing (Santorini, Greece, 7-9 May 2008). Proceedings, pp. 436 - 440. IEEE, 2008.
Caruso A., Chessa S., Maestrini P. - Worst-case diagnosis completeness in regular graphs under the PMC model. IEEE Transactions on Computers, vol. 56 (7) pp. 917 - 924. IEEE, 2007.
Robba A., Maestrini P. - Routing in Mobile Ad-hoc Networks: the Virtual Distance Vector Protocol. 4th IEEE Conference on Mobile Ad-hoc and Sensor Systems (Pisa, 8-11 October 2007). Proceedings, IEEE Computer Society, 2007.
Albini L.C.P.,
Caruso A., Chessa S., Maestrini P. - Reliable routing in wireless ad hoc
networks : the virtual routing protocol.
Journal of Network and Systems Management, vol. 14 (3) pp. 335-358. Springer,
2006.
Maestrini P. – La Calcolatrice Elettronica Pisana (CEP): una storia che sembra una leggenda. In L. Dadda Ed.: `La nascita dell`Informatica in Italia`, pp. 83- 96. Polipress, Milano, 2006.
Chessa S., Maestrini P. - Fault recovery mechanism in single-hop sensor networks. Computer communications, vol. 28 (17) pp. 1877-1886. Elsevier, 2005.
Di Pietro R., Chessa S., Maestrini P. - Computationally, memory and bandwidth efficient distillation codes to mitigate DoS in multicast. Securecomm (Atene, Grecia 5-9 Settembre 2005). Proceedings, pp. 20-30. IEEE, 2005.
Chessa S., Di Pietro R., Maestrini P. - Dependable and secure data storage in wireless ad hoc networks: an assessment of DS2. Working Conference on Wireless On-demand Network Systems (WONS 04) (Madonna di Campiglio, Trento, Italia, 21-23 January 2004). Proceedings, pp. 184-198. (Lecture Notes in Computer Science 2928). Springer, 2004.
Albini L. P. C., Chessa S., Maestrini P. - Diagnosis of symmetric graphs under the BGM model. The Computer Journal, 47 n.1 (2004), pp.85-92. Oxford University Press, 2004.
Caruso A., Albini L., Maestrini P. - A New Diagnosis Algorithm for Regular Interconnected Structures. First Latin American Symposium (Sao Paulo, Brasil, October 2003). Proceedings, pp. 263-281. Rogerio de Lemos et al. (eds.). (Lecture Notes in Computer Science 2847). Springer, 2003.
Caruso A., Chessa S., Maestrini P., Santi P. - Fault Diagnosis of Grid Structures. Theoretical Computer Science, 290 n.2 (2003), p. 1149-1174. Elsevier, 2003.
Chessa S., Maestrini P. - Dependable and Secure Data Storage and Retrieval in Mobile, Wireless Networks. IEEE DSN 2003, International Conference on Dependable System and Networks (San Francisco, USA, 22-25 June 2003). Proceedings, pp. 207-216. IEEE, 2003.
Caruso A., Chessa S., Maestrini P., Santi P. - Diagnosability of regular systems. Journal of Algorithms, 45 n. 2 (2002), 126-143. Elsevier, 2002.
Caruso A., Chessa S., Maestrini P., Santi P. - Evaluation of a diagnosis algorithm for regular structures. IEEE Transactions on Computers, Vol. 51 n. 7 (2002), 850-865. IEEE, 2002
Chessa S., Errico W., Maestrini P., Sallay B., Schifano F., Tripiccione R. - Self-diagnostic tools of the APEmille parallel machine. IEE Proceedings - Computers and Digital Techniques, 149, n. 6 (2002), 273-279. IEE, 2002.
Chessa S., Maestrini P. - Correct and almost complete diagnosis of processor grids. IEEE Transactions on Computers, Vol. 50 n. 10 (2001), 1095-1102. IEEE, 2001.
Caruso A., Chessa S., Maestrini P. - Comparison-based diagnosis of VLSI wafers. Design and Diagnostics of Electronic Circuits and Systems - 3rd DDECS Workshop (Smolenice Castle, Slovakia, April 5-7 2000). Proceedings, pp.227-232. IEEE Computer Society, 2000.
Caruso A., Chessa S., Maestrini P., Santi P. - Diagnosis of regular structures. International Conference on Dependable Systems and Networks - DSN 2000 (New York, 25-28 June 2000). Proceedings pp.213-222.
Caruso A., Chessa S., Maestrini P., Santi P. - Reliable diagnosis of grid-connected systems. IEEE - Latin American Test Workshop LATW'00 (Marina Palace Hotel, Rio de Janeiro, Brazil, 13-15 March 2000). Proceedings, pp.162-165. IEEE Computer Society, 2000.
Caruso A., Chessa S., Maestrini P. - Wafer-scale VLSI testing. Test Methods and Reliability of Circuits and Systems - 12th Workshop (Grassau, Germany, 19-21 March2000).
G.B. Gerace, L. Gilli, P. Maestrini, A.R. Meo, TOPI-A
special-purpose computer for boolean analysis and synthesis. IEEE
Transactions on Computers, vol C-20 n.8 (1971), pp. 837-842.
F. Barsi, P. Maestrini, Error-correcting properties of
redundant residue number systems. IEEE
Transactions on Computers, vol. C-22 n.3 (l973), pp. 307-315.
Reprinted
in: M. A. Soderstrand, W. K. Jenkins, A. Jullien and F. J. Taylor, eds: Residue
Number System Arithmetic: Modern Applications in Digital Signal Processing,
IEEE Computer Society Press, New York, 1986, pp. 352-360.
F. Barsi, P. Maestrini, Error detection and correction
by product codes in residue number systems.
IEEE Transactions on Computers, vol. C-23 n.9 (1974), pp. 915-924.
F. Barsi, P. Maestrini, A class of multiple error-correcting arithmetic residue codes. Information and Control, vol. 36 n.1 (1978), pp. 28-41.
F. Barsi, P. Maestrini, Improved decoding algorithms for arithmetic residue codes. IEEE Transactions on Information Theory, vol. IT-4 n.5
(1978), pp. 640-643.
F. Barsi, P. Maestrini, Arithmetic codes in residue
number systems with magnitude index. IEEE
Transactions on Computers, vol. C-27 n.12 (1978), pp. 1185-1188.
F. Barsi, P. Maestrini, Error codes constructed in
residue number systems with non-pairwise-prime moduli. Information and Control, vol. 46 n.1 (1980), pp. 16-25.
G. Alia, G. Frosini, P. Maestrini, Automated module
placement and wire routeing according to a structured biplanar scheme in
printed boards. Computer-Aided Design,
vol. 5 n.3 (1973), pp. 152-159.
G. Alia, P. Maestrini, An approach to optimal
partitioning of hypergraphs. Proceedings
of the 1974 ACM Annual Conference, San Diego, California, 1974, pp. 133-139.
M.A. Bonuccelli, E. Lodi, F. Luccio, P. Maestrini, L.
Pagli, A VLSI tree machine for relational data bases. Proc. 10.th IEEE Annual International Symposium on
Computer Architecture, Stockolm, 1983, pp. 67-73.
M. Schlag, F. Luccio, P. Maestrini, D.T. Lee, C.K. Wong, A
visibility problem in VLSI layout compaction.
In: F. P. Preparata, ed.: Advances in Computer Research, vol. II. JAI Press,
Greenwich, Connecticut, 1984, pp. 259-282.
M.A. Bonuccelli, E. Lodi, F. Luccio, P. Maestrini, L.
Pagli, VLSI algorithms and architecture for relational operations. Calcolo, vol. 22 n.1 (1985), pp. 63-90.
Reprinted
in: A.R. Hurson, L. L. Miller and S.H. Pakzad, eds.,Parallel architectures for
database systems, IEEE Computer Society Press, New York, 1989.
F. Barsi, F. Grandoni, P. Maestrini, Diagnosability of
systems partitioned into complex units.
Proceedings 5th IEEE International Symposium on Fault-tolerant Computing
(FTCS-5), Paris, 1975, pp. 171-175.
F. Barsi, F. Grandoni, P. Maestrini, A theory of
diagnosability of digital systems. IEEE
Transactions on Computers, vol. C-25 n.6 (1976), pp. 585-593.
C. L. Liu, P. Maestrini, On the sequential
diagnosability of a class of digital systems.
Proc. 11th IEEE International Symposium on Fault-tolerant Computing (FTCS-11),
Portland, Maine, 1981, pp. 112-115.
L. Baldelli, P. Maestrini, Diagnosis of Processor Arrays. Proc. 24th IEEE International Symposium on Fault-Tolerant
Computing (FTCS-24), Austin, Texas, 15-17 June 1994, pp. 48-54.
P. Maestrini, P. Santi, Self-Diagnosis of Processor
Arrays using a comparison model. Proc.
14.th Symposium on Reliable and Distributed Systems (SRDS-14), Bad Neuenahr,
Germany, pp.218-228, September 1995.
S. Chessa, P. Maestrini, Evaluation of Diagnosing
Algorithms for Grid Interconnected Systems,
DACP 96 International Workshop on Dependability in Advanced Computing
Paradigms, vol. 1, pp. 40-, Hitachi City, Ibaraki, Japan 1996
P. Maestrini, B. Sallay, P. Santi, A Comparison-Based
Diagnosis Algorithm Tolerating Comparator Faults. IEE
Proceedings-Computers and Digital Techniques, n¡ 4, vol. 146, pp. 211-, 1999
S. Chessa, B. Sallay, Maestrini, P., Diagnostic Model
and Diagnosis Algorithm of a SIMD Computer,
EDCC-3 Conference on Dependable Computing, Prague, vol. 1667, pp. 283-, Prague,
Czech Republic 1999
P. Maestrini, P. Santi, Self-Validating Diagnosis of
Hypercube Systems, 1999 IEEE Pacific Rim
International Symposium on Dependable Computing, vol. 1, pp. 228-236, Hong Kong
1999